PRODUCT 
MEMS Type
This is applicable to wafer test for CIS image and DRAM chips because signal noise is lower and electrical characteristics is stable, where the needles are generated from Si wafers which have high density needle array as a result of semiconductor lithography process.
- Optimum design for preventing yield drop
- Full wafer contact for 300mm wafer test
- Possibility of wafer test of DDR2, DDR3,
and GDDR5 chips
- Realized clock speed more than 1Gbps
- Cost reduction with multi-parallel test up
to 32 chips - Enabled multi-functional tests with both
logic and image device
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